A solution manual to Computer Architecture: A Quantitative by John L. Hennessy & David Patterson PDF

By John L. Hennessy & David Patterson

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B2: (S, 110, 00, 30), M[110]: (00, 30), read returns 30 e. B1: (I, 108, 00, 08) f. B2: (M, 130, 00, 78), M[110]: (00, 30) g. 2 a. 4 Chapter 4 Solutions ■ L-31 b. P0: read 100 Read miss, satisfied by memory P0: write 108 <-- 48 Write hit, sends invalidate P0: write 130 <-- 78 Write miss, satisfied by memory, write back 110 Implementation 1: 100 + 15 + 10 + 100 = 225 stall cycles Implementation 2: 100 + 15 + 10 + 100 = 225 stall cycles c. P1: read 120 Read miss, satisfied by memory P1: read 128 Read hit P1: read 130 Read miss, satisfied by memory Implementation 1: 100 + 0 + 100 = 200 stall cycles Implementation 2: 100 + 0 + 100 = 200 stall cycles d.

3% greater. 65 × 900 = 1485, so the DDR2-533 system is a better value. 0 CPI = 12 billion instructions per second. 00667 = 80 million level 2 misses per second. With the burst length of 8, this would be 80 × 32 bytes = 2560 MB/sec. 13 The power required to drive the output lines is the same in both cases, but the system built with the x4 DRAMs would require activating banks on 18 DRAMs, versus only 9 DRAMs for the x8 parts. The page size activated on each x4 and x8 part are the same and take roughly the same activation energy.

J. The exit branch of the while loop will likely cause branch prediction misses since the number of iterations taken by the while loop changes with every for loop iteration. Each such branch prediction miss disrupts the overlapped execution across for loop iterations. This means that the execution must reenter the steady state after the branch prediction miss is handled. It will introduce at least three extra cycles into total execution time, thus reducing the average level of ILP available. 5.

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A solution manual to Computer Architecture: A Quantitative Approach 4E (John L. Hennessy & David Patterson) by John L. Hennessy & David Patterson


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